DocumentCode
3364221
Title
SOI implementation of a 64-bit adder
Author
Tran, J.V. ; Mounes-Toussi, F. ; Storino, S.N. ; Stasiak, D.L.
Author_Institution
IBM Corp., Rochester, MN, USA
fYear
1999
fDate
1999
Firstpage
573
Lastpage
574
Abstract
Silicon-On-Insulator (SOI) technology allows for high performance by eliminating latch up in bulk CMOS, improving the short-channel effect, and soft error immunity. However, the floating body effect in SOI devices and the resulting hysteresis poses major challenges for dynamic circuit designers. In this paper, we describe implementation of a 64-bit adder and some of the techniques used to overcome the parasitic bipolar discharge effect while maintaining performance
Keywords
adders; silicon-on-insulator; 64 bit; 64-bit adder; SOI implementation; Silicon-On-Insulator; bulk CMOS; parasitic bipolar discharge; performance; Adders; CMOS technology; Copper; Integrated circuit interconnections; Microprocessors; Output feedback; State feedback; Switches; Switching circuits; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design, 1999. (ICCD '99) International Conference on
Conference_Location
Austin, TX
ISSN
1063-6404
Print_ISBN
0-7695-0406-X
Type
conf
DOI
10.1109/ICCD.1999.808598
Filename
808598
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