• DocumentCode
    3364345
  • Title

    Decomposition of finite state machines for area, delay minimization

  • Author

    Shelar, Rupesh S. ; Desai, Madhav P. ; Narayanan, H.

  • Author_Institution
    Dept. of Electr. Eng., Indian Inst. of Technol., Bombay, India
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    620
  • Lastpage
    625
  • Abstract
    We consider the state assignment problem as that of the decomposition of finite stare machines and transform this decomposition problem into an orthogonal partitioning problem with a certain cost function. We justify this cost function in two ways, first by using an idealized model of multi-level logic implementation, and second by empirical studies of a particular benchmark circuit. We describe a greedy algorithm to minimize this cost function. We present results obtained by running the algorithm on a set of 16 MCNC benchmarks. We compare these results with other state assignment techniques such as JEDI and NOVA. For multilevel implementations of the benchmark state machines, we find that the implementations obtained after using JEDI were, on average, 8.52% larger in area and 81.87% slower in delay than the implementations obtained using our approach. The implementations obtained after using NOVA were, on average, 4.40% larger in area and 104.96% slower in delay when compared with implementations obtained using our approach. Our scheme has the potential to serve as an alternative to conventional state assignment tools since we observe that it produces good results for larger finite state machines
  • Keywords
    delays; finite state machines; logic design; minimisation of switching nets; state assignment; JEDI; MCNC benchmarks; NOVA; area minimization; benchmark circuit; cost function; decomposition model; delay minimization; finite stare machine; finite state machines; greedy algorithm; idealized model; multi-level logic implementation; orthogonal partitioning problem; state assignment problem; Automata; Circuit synthesis; Costs; Delay; Digital systems; Minimization; Programmable logic arrays; Sequential circuits; Silicon; Tellurium;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design, 1999. (ICCD '99) International Conference on
  • Conference_Location
    Austin, TX
  • ISSN
    1063-6404
  • Print_ISBN
    0-7695-0406-X
  • Type

    conf

  • DOI
    10.1109/ICCD.1999.808606
  • Filename
    808606