Evaluation of de-scum methodology for through silicon via (TSV) etch to improve TSV defects performance

3D chip stacking are the solution for achieving more transistors on microchips. Through Si via (TSV) is the key for 2.5D and 3D technology. In this paper, a novel integrated de-scum technique are evaluated to improve both etch and litho process margin and TSV profile. Using a proper and optimized de-scum methodology for TSV etch we demonstrated a defect free TSV profile without any significant process integration impact and also throughput loss.