Iterative decimal multiplication using binary arithmetic

The IEEE-754 2008 standard for floating point arithmetic has definitely dictated the importance of decimal arithmetic. Human-centric applications, like financial and commercial, depend on decimal arithmetic since the results must match exactly those obtained by human calculations. A few hardware approaches have been proposed for decimal arithmetic, including addition, subtraction, multiplication and division. Parallel implementations for these operations are very expensive in terms of occupied resources and therefore implementations based on iterative algorithms are good alternatives. In this paper, we propose an iterative decimal multiplier for FPGA that uses binary arithmetic. The circuits were implemented in a Xilinx Virtex 4 FPGA. The results indicate that the proposed iterative multipliers are very competitive when compared to decimal multipliers implemented with direct manipulation of BCD numbers.