Stress analysis of Si lattice near TSV structures

As a result of differences in coefficient of thermal expansion (CTE), Cu-filled TSV induces strain in the Si lattice surrounding it. Strain can have significant impact on the electrical performance of the logic transistors. Therefore, it is essential to investigate the induced strain in the Si lattice around TSV structures. Conventional strain characterization techniques are only able to detect strain at micron-level resolutions. In this work, we demonstrated the use of HRTEM to extract the lateral and vertical strain profile in the Si lattice around the TSV with a detection resolution of 10nm. This serves to provide more detailed information on the strain profiles within the close vicinity (<;100nm) of the TSVs as their dimensions are scaled beyond the micron-regime.