DocumentCode :
3365316
Title :
A VLSI architecture for a Run-time Multi-precision Reconfigurable Booth Multiplier
Author :
Shun, Zhou ; Pfänder, Oliver A. ; Pfleiderer, Hans-Jörg ; Bermak, Amine
Author_Institution :
Hong Kong Univ. of Sci. & Technol., Hong Kong
fYear :
2007
fDate :
11-14 Dec. 2007
Firstpage :
975
Lastpage :
978
Abstract :
In this paper, a reconflgurable multi-precision Radix-4 Booth multiplier structure is presented. The reconfig- urable 8 x 8 bit multiplier unit can be cascaded to form a multiplier that can adapt to variable input precision requirements. The number of bits can be extended by concatenating more stages together. For example, four 8 x8 bit units can be used to build a 16 x 16 bit Booth multiplier. In our proposed architecture, the multiplier adapts to different bit-lengths by using external control signals. The performance of our reconflgurable multiplier are compared with a parallel array multiplier and a conventional Booth multiplier. The comparison is based on synthesis results obtained by synthesizing all multiplier architectures targeting a Xilinx FPGA. The overhead resulting from our reconfiguration scheme are also evaluated and compared to a conventional Booth and array multipliers.
Keywords :
VLSI; field programmable gate arrays; multiplying circuits; Radix-4; VLSI architecture; Xilinx FPGA; reconflgurable multiplier; run-time multi-precision reconfigurable booth multiplier; Computer architecture; Delay; Digital signal processing; Energy consumption; Field programmable gate arrays; Runtime; Signal processing algorithms; Signal synthesis; Silicon; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
Conference_Location :
Marrakech
Print_ISBN :
978-1-4244-1377-5
Electronic_ISBN :
978-1-4244-1378-2
Type :
conf
DOI :
10.1109/ICECS.2007.4511155
Filename :
4511155
Link To Document :
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