MIC@R : A Generic Low Latency Router for On-Chip Networks

The design of efficient router represents a key issue for the success of the Network-on-chip approach. This paper presents and evaluates a novel router architecture MIC@R suitable for Networks-on-Chip (NoC) Design. This router offers lowest latency (1 cycle) and allows supporting several adaptive routing algorithms. Latency reduction is obtained by using Fast Parallel Routing (FPR) arbitration that consists in parallel processing -in one stage, routing decisions and arbitration. The proposed router architecture is evaluated in 2D Mesh with two adaptive routing algorithms: fully adaptive (FA) and Proximity Congestion Awareness (PCA). The obtained results show that our router, combined with adaptive routing techniques is effective in terms of latency and throughput.