Title :
Parallel adders using standard plas
Author :
Weinberger, Arnold
Author_Institution :
Int. Bus. Machines Corp., Poughkeepsie, NY, USA
Abstract :
PLA adders are described that add in one cycle and require a reasonable number of product terms for an 8, 16, or even a 32-bit adder. A procedure is also described for minimizing the number of product terms for any size adder.
Keywords :
adders; programmable logic arrays; 16-bit adder; 32-bit adder; 8-bit adder; PLA adders; parallel adders; product terms minimization; programmable logic arrays; Adders; Arrays; Bismuth; Decoding; Equations; Indexes; Programmable logic arrays; Programmable Logic Array (PLA); adder; carry-look-ahead; input decoders; output exclusive-ORs; product term minimization;
Conference_Titel :
Computer Arithmetic (ARITH), 1978 IEEE 4th Symposium on
Conference_Location :
Santa Monica, CA
DOI :
10.1109/ARITH.1978.6155761
