Ultra low power analog standard cell for low frequency CMOS filters design

Author

Kulej, Tomasz

Author_Institution

Dept. of Electr. Eng., Tech. Univ. of Czestochowa, Czestochowa

fYear

2008

fDate

14-17 Sept. 2008

Firstpage

69

Lastpage

72

Abstract

A novel approach to very low frequency filters design in CMOS technology has been described in the paper. This approach is based on the application of a new universal analog cell, which can be configured as second order filter, gyrator etc. The circuit is designed in 0.35 mum n-well technology and consumes only 3 nW of power for nominal biasing current. The supply voltage is equal to 1 V with additional auxiliary biasing voltage equal to -1 V. The performance is verified by SPICE simulations.

Keywords

CMOS analogue integrated circuits; SPICE; active filters; integrated circuit design; low-power electronics; SPICE simulations; active filter design; auxiliary biasing voltage; low-frequency CMOS filters design; n-well technology; power 3 nW; size 0.35 mum; ultra-low power analog standard cell; universal analog cell; voltage -1 V; voltage 1 V; Active filters; CMOS technology; Charge pumps; Circuits; Frequency; MOSFETs; Transconductance; Transconductors; Variable structure systems; Voltage; Bulk-driven circuits; Low-frequency filters;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals and Electronic Systems, 2008. ICSES '08. International Conference on

Conference_Location

Krakow

Print_ISBN

978-83-88309-47-2

Electronic_ISBN

978-83-88309-52-6

Type

conf

DOI

10.1109/ICSES.2008.4673360

Filename

4673360