Title :
Minimum power-delay product design of MCML gates
Author :
Caruso, Giuseppe ; Macchiarella, Alessio
Author_Institution :
Dipt. di Ing. Elettr. Elettron. e delle Telecomun., Univ. di Palermo, Palermo
Abstract :
This paper describes a methodology for the minimization of the power-delay product of MCML gates. The method is based on the novel concept of crossing point capacitance. The methodology was been validated by designing several gates using in an IBM 130 nm CMOS process.
Keywords :
CMOS logic circuits; current-mode logic; logic design; logic gates; CMOS process; MCML gates; MOS current mode logic circuits; crossing point capacitance; power-delay product design; size 130 nm; CMOS logic circuits; CMOS process; Delay; MOSFETs; Minimization methods; Parasitic capacitance; Product design; Resistors; Telecommunications; Voltage; MCML; MOS current-mode logic gates; design; power-delay product;
Conference_Titel :
Signals and Electronic Systems, 2008. ICSES '08. International Conference on
Conference_Location :
Krakow
Print_ISBN :
978-83-88309-47-2
Electronic_ISBN :
978-83-88309-52-6
DOI :
10.1109/ICSES.2008.4673370
