An analytical model of multilevel ILD thickness variation induced by the interaction of layout pattern and CMP process

Author

Ryu, Kyungsuk ; Ouyang, Charles ; Milor, Linda ; Maly, Wojeiech ; Hill, Gene ; Peng, Yeng

Author_Institution

Carnegie Mellon Univ., Pittsburgh, PA, USA

fYear

1999

fDate

1999

Firstpage

221

Lastpage

224

Abstract

In this paper, an analytical model for Chemical Mechanical Polishing (CMP) is proposed. This model relates the physical parameters of the CMP process to the in-die variation of Inter-Layer Dielectric (ILD) in the multilevel metal process. The physical parameters considered in this model include the deposited ILD profile, deformation of the polishing pad and the hydrodynamic pressure of slurry flow. We demonstrate a fit with sample data at the die level of a state-of-the-art microprocessor

Keywords

CMOS digital integrated circuits; chemical mechanical polishing; dielectric thin films; integrated circuit interconnections; integrated circuit layout; integrated circuit metallisation; microprocessor chips; semiconductor process modelling; thickness control; CMP process; analytical model; chemical mechanical polishing; deposited ILD profile; dielectric profile; high density CMOS circuits; in-die variation; interlayer dielectric; layout pattern; microprocessor; multilevel ILD thickness variation; multilevel metal process; physical parameters; polishing pad deformation; slurry flow hydrodynamic pressure; Analytical models; CMOS process; Capacitance; Databases; Dielectric films; Hydrodynamics; Integrated circuit layout; Slurries; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Manufacturing Conference Proceedings, 1999 IEEE International Symposium on

Conference_Location

Santa Clara, CA

ISSN

1523-553X

Print_ISBN

0-7803-5403-6

Type

conf

DOI

10.1109/ISSM.1999.808776

Filename

808776