DocumentCode
3368083
Title
Analysis and architecture design for high performance JPEG2000 coprocessor
Author
Wu, Bing-Fei ; Lin, Chung-Fu
Author_Institution
Dept. of Electr. & Control Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume
2
fYear
2004
fDate
23-26 May 2004
Abstract
The high throughput and less internal memory requirement are two key issues of integrating the JPEG2000 encoding system. For this bottleneck of integration, a QCB (quad code block)-based DWT method is proposed to achieve more efficient parallelism in the JPEG2000 coprocessor. Based on the QCB-based DWT engine, the code blocks can be completely generated after every fixed time slice, recursively. Thus, the overall JPEG2000 encoding system arrives higher parallelism between DWT and EBCOT processors and thus preserves the high throughput, as DWT does. By changing the output timing of the DWT process and parallelizing with EBCOT, the internal tile memory size can be reduced by a factor of 4. Moreover, with smoother encoding flow of overall encoding system, the memory access cycles between the internal tile memory and code block memory also decreases.
Keywords
block codes; coprocessors; discrete wavelet transforms; image coding; EBCOT processors; JPEG2000 coprocessor; JPEG2000 encoding system; code block memory; discrete wavelet transform engine; internal tile memory; memory access cycles; quad code block; Coprocessors; Degradation; Discrete wavelet transforms; Hardware; Image coding; Performance analysis; Streaming media; Throughput; Tiles; Transform coding;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN
0-7803-8251-X
Type
conf
DOI
10.1109/ISCAS.2004.1329249
Filename
1329249
Link To Document