A novel fast low voltage dynamic threshold true single phase clocking adiabatic circuit

Author

Yang, Michael M. ; Barby, James A.

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

A novel fast true single phase clocking (TSPC) adiabatic differential logic circuit using dynamic threshold (DTMOS) is proposed (DT-TSPC-A). It is capable of operating at 0.7 V. The performance of four circuit architectures (DT-TSPC-A, conventional static CMOS logic, and two other published adiabatic circuits) is compared using a four inverter chain as the test circuit. At 50 MHz and 0.8 V with 20 fF load, this circuit consumes the least amount of energy of the four circuit architectures compared. It takes about the same area and consumes 55% less energy than the static circuit. It has the shortest delay and is 56% faster than other adiabatic circuits and takes at most 2.3 times the area. In addition results for more complex circuits are supplied demonstrating the improved performance of DT-TSPC-A circuits.

Keywords

CMOS logic circuits; circuit simulation; invertors; low-power electronics; 0.8 V; 50 MHz; adiabatic circuit; adiabatic differential logic circuit; circuit architecture; complex circuit; conventional static CMOS logic; dynamic threshold; fast true single phase clocking; four inverter chain; shortest delay; static circuit; CMOS logic circuits; Circuit testing; Clocks; Delay; Energy consumption; Inverters; Logic circuits; Logic testing; Low voltage; MOS devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329265

Filename

1329265