A novel memory-based FFT processor for DMT/OFDM applications

Author

Chang, Ching-Hsien ; Wang, Chin-Liang ; Chang, Yu-Tai

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

Volume

4

fYear

1999

fDate

15-19 Mar 1999

Firstpage

1921

Abstract

This paper presents a novel VLSI architecture for computing the N-point discrete Fourier transform (DFT) based on a radix-2 fast algorithm, where N is a power of two. The architecture consists of one complex multiplier, two complex adders, and some special memory units. It can compute one transform sample every log₂N+1 clock cycles in average. For the case of N=512, the chip area required is about 5742×5222 μm² and the throughput is up to 4 M transform samples per second under 0.6 μm CMOS technology. Such area-time performance makes the proposed design rather attractive for use in long-length DFT applications, such as ADSL and OFDM systems

Keywords

CMOS logic circuits; CMOS memory circuits; OFDM modulation; VLSI; adders; digital arithmetic; digital signal processing chips; digital subscriber lines; fast Fourier transforms; multiplying circuits; random-access storage; read-only storage; 0.6 micron; ADSL; CMOS technology; DFT; DMT/OFDM applications; N-point discrete Fourier transform; RAM; ROM; VLSI; VLSI architecture; area-time performance; chip area; clock cycles; complex adders; complex multiplier; long-length DFT applications; memory units; memory-based FFT processor; radix-2 fast algorithm; throughput; transform sample; CMOS technology; Clocks; Computer architecture; Discrete Fourier transforms; Discrete transforms; Matrix decomposition; OFDM modulation; Power engineering computing; Signal processing algorithms; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1999. Proceedings., 1999 IEEE International Conference on

Conference_Location

Phoenix, AZ

ISSN

1520-6149

Print_ISBN

0-7803-5041-3

Type

conf

DOI

10.1109/ICASSP.1999.758300

Filename

758300