Design of low-leakage power-rail ESD clamp circuit with MOM capacitor and STSCR in a 65-nm CMOS process

Author

Chiu, Po-Yen ; Ker, Ming-Dou

Author_Institution

Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan

fYear

2011

fDate

2-4 May 2011

Firstpage

1

Lastpage

4

Abstract

A power-rail electrostatic discharge (ESD) clamp circuit designed with low-leakage consideration has been proposed and verified in a 65-nm low-voltage CMOS process. By using the metal-oxide-metal (MOM) capacitor in the ESD-detection circuit, the power-rail ESD clamp circuit realized with only thin-oxide (1-V) devices has very low stand-by leakage current, as compared to the traditional design. The experimental results in the silicon chip showed that the standby leakage current is only 358 nA at room temperature (25°C) under the power-supply voltage of 1 V, whereas the traditional design realized with the NMOS capacitor is as high as 828 μA under the same bias condition.

Keywords

CMOS integrated circuits; MIM devices; capacitors; electrostatic discharge; leakage currents; network synthesis; power aware computing; CMOS process; ESD clamp circuit; ESD-detection circuit; MOM capacitor; NMOS capacitor; leakage current; low-leakage consideration; low-leakage power-rail ESD clamp circuit; metal-oxide-metal capacitor; power-rail electrostatic discharge; power-supply voltage; silicon chip; size 65 nm; temperature 25 degC; voltage 1 V; Capacitors; Clamps; Electrostatic discharge; Leakage current; Logic gates; MOS capacitors; Moment methods;

fLanguage

English

Publisher

ieee

Conference_Titel

IC Design & Technology (ICICDT), 2011 IEEE International Conference on

Conference_Location

Kaohsiung

ISSN

Pending

Print_ISBN

978-1-4244-9019-6

Type

conf

DOI

10.1109/ICICDT.2011.5783185

Filename

5783185