Fault-tolerant architecture for nanoelectronic digital logic

This paper presents a new system architecture for implementing fault-tolerant information processing. The proposed structure relies on simple processing elements (PEs) arranged into a regular locally-interconnected array. Such an approach is a favorable way of implementing circuits with inherently unreliable nanodevices. Different network operations are achieved through binary programmable interconnections. The array can be divided into a set of software-defined segments for implementing functions with different levels of complexity and redundancy, assuring the system versatility and flexibility. The examples of basic Boolean operations are presented. The error correction mechanism is explained and its impact on fault-tolerance is briefly analyzed.