A single TSV-rail 3D quasi delay insensitive asynchronous signaling

Author

Belleville, M. ; Beigne, E. ; Valentian, A.

Author_Institution

LETI, CEA, Grenoble, France

fYear

2011

fDate

2-4 May 2011

Firstpage

1

Lastpage

4

Abstract

Asynchronous communications are foreseen as mandatory for implementing 3D multiple tiers circuits. The drawback of asynchronous rails compared to synchronous ones is the higher number of interconnects. This number needs to be decreased when horizontal interconnects are replaced by Through Silicon Vias (TSV) because of their big silicon footprint. A circuit using only one TSV for asynchronous, quasi delay insensitive 3D signal propagation is proposed. This achieves to save two TSVs out of three, while offering 1Gbits/s capability.

Keywords

asynchronous circuits; three-dimensional integrated circuits; asynchronous communications; asynchronous rails; quasi-delay insensitive 3D signal propagation; silicon footprint; single TSV-rail 3D quasi-delay insensitive asynchronous signaling; through silicon vias; Bismuth; Delay; Integrated circuit interconnections; Silicon; Three dimensional displays; Through-silicon vias; Transmitters; 3D Integration; Globally Asynchronous Locally Synchronous; Quasi Delay Insensitive; Through Silicon Via;

fLanguage

English

Publisher

ieee

Conference_Titel

IC Design & Technology (ICICDT), 2011 IEEE International Conference on

Conference_Location

Kaohsiung

ISSN

Pending

Print_ISBN

978-1-4244-9019-6

Type

conf

DOI

10.1109/ICICDT.2011.5783201

Filename

5783201