DocumentCode
3370202
Title
Gate-driven 3.3V ESD clamp using 1.8V transistors
Author
Wang, Guang-Cheng ; Chen, Chia-Hui ; Huang, Wen-Hsin ; Chen, Kuo-Ji ; Song, Ming-Hsiang ; Guo, Ta-Pen
Author_Institution
Taiwan Semicond. Manuf. Corp., Hsinchu, Taiwan
fYear
2011
fDate
2-4 May 2011
Firstpage
1
Lastpage
4
Abstract
A new gate driven 3.3V ESD clamp circuit using 1.8V transistor is proposed. This new clamp circuit is suitable for ESD protection of legacy 3.3V I/O interface circuit in SOC chips which use only 1.8V I/O transistors. This clamp along with 3.3V I/O have been demonstrated in 40nm 1.8V process. Life-time test can pass 1000-hours prolonged operation. ESD/Latch-up can pass HBM 3KV, MM 300V, and +/-200mA current triggering and 4.95V (1.5 × VDD) over-voltage test.
Keywords
electrostatic discharge; life testing; logic gates; system-on-chip; transistors; ESD protection; SOC chip; gate driven ESD clamp circuit; legacy interface circuit; life-time test; size 40 nm; time 1000 hr; transistors; voltage 1.8 V; voltage 3 kV; voltage 3.3 V; voltage 300 V; voltage 4.95 V; Clamps; Electrostatic discharge; Logic gates; Rails; Resistors; System-on-a-chip; Transistors; gate oxide over-stress; gate-driven; human-body model (HBM); machine model (MM);
fLanguage
English
Publisher
ieee
Conference_Titel
IC Design & Technology (ICICDT), 2011 IEEE International Conference on
Conference_Location
Kaohsiung
ISSN
Pending
Print_ISBN
978-1-4244-9019-6
Type
conf
DOI
10.1109/ICICDT.2011.5783234
Filename
5783234
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