Design and implementation of synchronization detection for IEEE 802.15.3c

Author

Huang, Ya-Shiue ; Liu, Wei-Chang ; Jou, Shyh-Jye

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2011

fDate

25-28 April 2011

Firstpage

1

Lastpage

4

Abstract

In this paper, a jointed preamble/boundary detection and fractional carrier frequency offset (CFO) estimation design is presented which supports dual SC/HSI modes of IEEE 802.15.3c applications. Based on correlation based algorithms which utilizes the structure of preamble, an efficiency architecture is proposed which realizes synchronization detection with a sequential detection scheme and only single hardware for dual modes and three detection operations. In order to achieve the requirement of sampling rate, the architecture is 8x parallelism and operates at 330 MHz clock rate. The total gate count is 189k in 65 nm 1P9M CMOS process with power consumption of 60.16 mW including memory elements which occupies 63.26% and can be shared with the frequency domain equalizer (FDE).

Keywords

CMOS integrated circuits; frequency estimation; personal area networks; CFO estimation design; CMOS process; FDE; IEEE 802.15.3c; correlation based algorithm; dual SC-HSI mode; fractional carrier frequency offset; frequency 330 MHz; frequency domain equalizer; power 60.16 mW; preamble-boundary detection; sequential detection scheme; size 65 nm; synchronization detection; Computer architecture; Correlation; Delay; Estimation; Logic gates; OFDM; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on

Conference_Location

Hsinchu

ISSN

Pending

Print_ISBN

978-1-4244-8500-0

Type

conf

DOI

10.1109/VDAT.2011.5783583

Filename

5783583