• DocumentCode
    3372545
  • Title

    Gate-Exhaustive and Cell-Aware pattern sets for industrial designs

  • Author

    Hapke, Friedrich ; Schloeffel, Juergen ; Hashempour, Hamidreza ; Eichenberger, Stefan

  • Author_Institution
    Mentor Graphics, Hamburg, Germany
  • fYear
    2011
  • fDate
    25-28 April 2011
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Industry is facing very high quality requirements for today´s and tomorrow´s ICs. Especially in the automotive market these quality requirements need to be fulfilled. To achieve this, we need to improve currently used test methods and fault models to improve the overall defect coverage. This paper presents achieved results from 1500 CMOS 65nm library cells and from 10 industrial designs applying Gate-Exhaustive and defect oriented Cell-Aware pattern sets.
  • Keywords
    CMOS integrated circuits; automotive electronics; fault location; automotive market; cell-aware pattern sets; fault models; gate-exhaustive; industrial designs; quality requirements; test methods; Automatic test pattern generation; Bridges; CMOS integrated circuits; Circuit faults; Libraries; Logic gates; Semiconductor device modeling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on
  • Conference_Location
    Hsinchu
  • ISSN
    Pending
  • Print_ISBN
    978-1-4244-8500-0
  • Type

    conf

  • DOI
    10.1109/VDAT.2011.5783604
  • Filename
    5783604
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3372545