• DocumentCode
    3372564
  • Title

    A hybrid-type test pattern generating mechanism

  • Author

    Chen, Chuen-Yau ; Hsu, An-Chi

  • Author_Institution
    Dept. of Electr. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan
  • Volume
    5
  • fYear
    2004
  • fDate
    23-26 May 2004
  • Abstract
    We blend the weighted-random-pattern generator and the controllable-linear-feed-back-shift register to develop a hybrid-type test pattern generating mechanism. The whole testing is performed in two phase. The weighted-random-pattern generator drops some of the faults from the fault list during the first phase. Remaining faults will be tested by the controllable-linear-feed-back-shift register to generate the deterministic patterns instead of modifying the configuration of the weighted-random-pattern generator such that a better fault coverage can be achieved with a lower hardware penalty and a shorter test length.
  • Keywords
    automatic test pattern generation; fault simulation; shift registers; controllable-linear-feed-back-shift register; deterministic pattern; fault coverage; fault list; hardware penalty; test length; test pattern generating mechanism; weighted-random-pattern generator; Automatic testing; Bismuth; Built-in self-test; Circuit faults; Circuit testing; Cities and towns; Hardware; Linear feedback shift registers; System-on-a-chip; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
  • Print_ISBN
    0-7803-8251-X
  • Type

    conf

  • DOI
    10.1109/ISCAS.2004.1329503
  • Filename
    1329503