• DocumentCode
    3372708
  • Title

    Inconsistent Fail due to Limited Tester Timing Accuracy

  • Author

    Park, Intaik ; Lee, Donghwi ; Chmelar, Erik ; McCluskey, Edward J.

  • Author_Institution
    Center for Reliable Comput., Stanford Univ., Stanford, CA
  • fYear
    2008
  • fDate
    April 27 2008-May 1 2008
  • Firstpage
    47
  • Lastpage
    52
  • Abstract
    Delay testing is a technique to determine if a chip will function correctly at a specified frequency. If a chip passes delay tests, it will presumably function at the specified frequency in the field. This paper presents experimental results that show how chips can pass very thorough delay tests and still fail in the field. It is shown that some chips sometimes pass and sometimes fail when the same delay test is applied multiple times under the same test conditions. These chips are called inconsistent fails. This paper shows how tester timing edge placement accuracy can cause inconsistent fails and suggests the minimum requirements for guardbands that avoid the inconsistent test results.
  • Keywords
    integrated circuit testing; IC delay testing; tester timing edge placement accuracy; Accuracy; Circuit testing; Delay; Flip-flops; Frequency; Integrated circuit testing; Logic testing; Temperature; Timing; Voltage; delay test; inconsistency; inconsistent fail; tester EPA; tester timing accuracy;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 2008. VTS 2008. 26th IEEE
  • Conference_Location
    San Diego, CA
  • ISSN
    1093-0167
  • Print_ISBN
    978-0-7695-3123-6
  • Type

    conf

  • DOI
    10.1109/VTS.2008.23
  • Filename
    4511695