A minimal-gate-count fully digital frequency-tracking oversampling CDR circuit

Author

Sarmento, José ; Stonick, John T.

fYear

2010

fDate

May 30 2010-June 2 2010

Firstpage

2099

Lastpage

2102

Abstract

In this paper, a fully digital frequency-tracking clock and data recovery circuit is presented. The circuit is implemented in a commercial USB 2.0 transceiver platform, and adopts a new clock phase selection feedback approach rather than the conventional feed-forward blind oversampling methodology. This allows for frequency-tracking capability. In spite of the feedback loop used, the circuit is implemented in an entirely digital design flow, allowing for a minimized gate count and power consumption. Formal analysis of the circuit paths allows for ease-of-reuse and retargeting, and is also presented in detail.

Keywords

clock and data recovery circuits; signal processing equipment; transceivers; USB 2.0; data recovery circuit; digital design; fully digital frequency tracking CDR circuit; fully digital frequency tracking clock circuit; minimal gate count CDR circuit; oversampling CDR circuit; transceiver platform; CMOS process; Clocks; Feedback circuits; Feedback loop; Feedforward systems; Frequency; Multiplexing; Phase locked loops; Transceivers; Universal Serial Bus;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Conference_Location

Paris

Print_ISBN

978-1-4244-5308-5

Electronic_ISBN

978-1-4244-5309-2

Type

conf

DOI

10.1109/ISCAS.2010.5537061

Filename

5537061