DocumentCode :
3372804
Title :
On the Detectability of Scan Chain Internal Faults An Industrial Case Study
Author :
Yang, F. ; Chakravarty, S. ; Devta-Prasanna, N. ; Reddy, S.M. ; Pomeranz, I.
Author_Institution :
Univ. of Iowa, Iowa City, IA
fYear :
2008
fDate :
April 27 2008-May 1 2008
Firstpage :
79
Lastpage :
84
Abstract :
Scan chains contain approximately 50% of the logic transistors in large industrial designs. Yet, faults in the scan cells are not directly targeted by scan tests and assumed detected by flush tests. Reported results of targeting the scan cell internal faults using checking sequences show such tests to be about 4.5 times longer than scan stuck-at test sets and require a sequential test generator, even for full scan circuits. We present the first step in developing an alternative test methodology for scan cell internal faults. Fault detection capability of existing tests (flush tests, stuck-at tests and transition delay fault tests) are quantified. Existing tests are shown to have similar coverage as checking sequences. A new flush test, viz. half-speed flush test, is defined. This new test is shown to add 2.3% and 8.8% to the stuck-at and stuck-on fault coverage, respectively.
Keywords :
fault diagnosis; flip-flops; logic testing; checking sequences; fault detection; flip-flops; flush tests; logic transistors; scan chain internal faults; scan stuck-at test; scan tests; sequential test generator; stuck-on fault coverage; transition delay fault tests; Automatic test pattern generation; Circuit faults; Circuit testing; Cities and towns; Electrical fault detection; Fault detection; Flip-flops; Latches; Logic design; Sequential analysis; Faults in scan cells; stuck-at and stuck-on faults;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2008. VTS 2008. 26th IEEE
Conference_Location :
San Diego, CA
ISSN :
1093-0167
Print_ISBN :
978-0-7695-3123-6
Type :
conf
DOI :
10.1109/VTS.2008.13
Filename :
4511700
Link To Document :
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