Design of complementary low-power CMOS architectures for looser-take-all and winner-take-all

Author

Donckers, Nicolas ; Dualibe, Carlos ; Verleysen, Michel

Author_Institution

Microelectron. Lab., Univ. Catholique de Louvain, Belgium

fYear

1999

fDate

1999

Firstpage

360

Lastpage

365

Abstract

A novel architecture for winner-take-all (WTA) and looser-take-all (LTA) circuits is proposed. As compared with other realisations, the LTA does not require input subtraction from a reference, which decreases accuracy and input dynamics. The architectures have been designed using the g_m/I_D methodology. It is shown that this method allows a rapid new dimensioning when specifications are modified. Both the WTA and the LTA can operate with low voltage supply, and show better speed characteristics (delay and rise time) for a 6 bits accuracy and a typical consumption of 50 μW/cell than previous realisations

Keywords

CMOS analogue integrated circuits; analogue computer circuits; analogue processing circuits; integrated circuit design; low-power electronics; neural chips; LTA circuits; WTA circuits; analog neural network application; analogue processor applications; complementary low-power CMOS architectures; delay; g_m/I_D methodology; looser-take-all circuits; low voltage supply; rise time; speed characteristics; top-down methodology; winner-take-all circuits; Analog computers; Circuits; Computer architecture; Computer interfaces; Computer networks; Concurrent computing; Delay; Laboratories; Low voltage; Microelectronics;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro '99. Proceedings of the Seventh International Conference on

Conference_Location

Granada

Print_ISBN

0-7695-0043-9

Type

conf

DOI

10.1109/MN.1999.758887

Filename

758887