A 1.6 GHz dual-core ARM Cortex A9 implementation on a low power high-K metal gate 32nm process

Author

Koppanalil, Jinson ; Yeung, Gus ; Driscoll, Dermot O. ; Householder, Sean ; Hawkins, Chris

Author_Institution

Processor Div., ARM Inc., Austin, TX, USA

fYear

2011

fDate

25-28 April 2011

Firstpage

1

Lastpage

4

Abstract

This paper discusses the implementation details and silicon result of a 1.6 GHz dual-core Cortex-A9 on a low power High-K Metal Gate 32 nm CMOS Bulk Process. The implementation is based on a fully synthesizable flow utilizing ARM Standard Cell and Memory IP. The completed design includes power gating and Dynamic Voltage Frequency Scaling capabilities for low static and dynamic power consumption and achieves beyond GHz+ nominal operating frequency. This paper will outline the chip architecture, discuss the implementation and challenges encountered during design and present results measured from the functional silicon.

Keywords

CMOS integrated circuits; elemental semiconductors; high-k dielectric thin films; integrated memory circuits; low-power electronics; microprocessor chips; silicon; ARM standard cell; CMOS bulk process; Si; chip architecture; dual-core ARM Cortex A9 implementation; dynamic power consumption; dynamic voltage frequency scaling; frequency 1.6 GHz; low power high-k metal gate; low static power consumption; memory IP; power gating; silicon; size 32 nm; Clocks; Computer architecture; Logic gates; Metals; Microprocessors; Random access memory; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on

Conference_Location

Hsinchu

ISSN

Pending

Print_ISBN

978-1-4244-8500-0

Type

conf

DOI

10.1109/VDAT.2011.5783620

Filename

5783620