A highly linear monolithic CMOS detector for computed tomography

Computed tomography (CT) requires high-speed detector with wide dynamic range (WDR) and high linearity. CMOS CT detectors have been demonstrated with WDR and quantum-limited noise. However, existing CMOS CT detectors have low linearity, which cause artifacts during the image reconstruction. They also require high-resolution off-chip analog-to-digital converter (ADC) to quantize the WDR. In this work, a new synchronous partial quantization technique is developed for highly-linear CMOS CT detectors. System-level and circuit-level innovations enable the new detector to extend the dynamic range with constant potential well size, which results in high linearity. The new monolithic detector includes a low-resolution ADC to quantize the residual voltage. A prototype detector is fabricated in a 0.35 μm CMOS process. The new detector has 75.5% geometrical detective quantum efficiency with the ADC and the voltage reference. Measurements show the detector can quantize signal currents from 6 pA to 63.4 nA with relative deviation lower than 0.06% at 1.1 kHz frame rate, which removes the detector-induced artifacts after the image reconstruction. The electronic noise of the detector is smaller than the X-ray Poisson noise in the whole signal range. The minimum detector noise is 0.6 pA_rms. As a result, the detector achieves 16.7 bits dynamic range.