DocumentCode
3373164
Title
Generating random benchmark circuits for floorplanning
Author
Wan, Tao ; Chrzanowska-Jeske, Malgorzata
Author_Institution
Dept. of Electr. & Comput. Eng., Portland State Univ., OR, USA
Volume
5
fYear
2004
fDate
23-26 May 2004
Abstract
Benchmark files are widely used to evaluate and compare new algorithms and tools. In this paper, a fairly simple although reliable random floorplanning benchmark generator, BGen, based on Rent´s rule and a novel net-degree distribution model, is presented. Though direct and indirect validation, it is shown that BGen generates realistic distribution of module sizes and netlist information.
Keywords
VLSI; benchmark testing; circuit layout CAD; integrated circuit layout; modules; BGen; benchmark files; floorplanning benchmark generator; module size distribution; net-degree distribution model; netlist information; random benchmark circuits generation; Algorithm design and analysis; Area measurement; Benchmark testing; Circuit testing; Field programmable gate arrays; Integrated circuit interconnections; Logic; Power dissipation; Power generation; Shape;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN
0-7803-8251-X
Type
conf
DOI
10.1109/ISCAS.2004.1329533
Filename
1329533
Link To Document