Test-Pattern Ordering for Wafer-Level Test-During-Burn-In

Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significant power variations in a die during test-pattern application. This variation adversely affects the accuracy of predictions of junction temperatures and the time required for burn-in. We present a test-pattern ordering technique for WLTBI, where the objective is to minimize the variation in power consumption during test application. The test-pattern ordering problem for WLTBI is formulated and it is solved using an efficient heuristic technique. Simulation results are presented for the ISCAS´89 and the IWLS´05 benchmark circuits, and the proposed ordering technique is compared with two baseline methods that carry out pattern-ordering to minimize peak power and average power, respectively. A third baseline method that randomly orders test patterns is also used to evaluate the proposed methods.