Title :
Dynamic Compaction for High Quality Delay Test
Author :
Wang, Zheng ; Walker, D.M.H.
Author_Institution :
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX
fDate :
April 27 2008-May 1 2008
Abstract :
Dynamic compaction is an effective way to reduce the number of test patterns while maintaining high fault coverage. This paper proposes a new dynamic compaction algorithm for generating compacted test sets for K longest paths per gate (KLPG) in combinational circuits or scan-based sequential circuits. This algorithm uses a greedy approach to compact paths with non-conflicting assignments together during test generation. Experimental results for ISCAS89 benchmark circuits and two industry circuits show that the pattern count of KLPG can be significantly reduced (up to 3x compared to static compaction) using the proposed method. The pattern count after dynamic compaction is comparable to the number of transition fault tests, while achieving higher test quality.
Keywords :
automatic test pattern generation; combinational circuits; greedy algorithms; logic gates; logic testing; sequential circuits; ISCAS89 benchmark circuits; K longest paths per gate; combinational circuits; compacted test set generation; dynamic compaction; fault coverage; greedy approach; high quality delay test; industry circuits; scan-based sequential circuits; test patterns; transition fault tests; Automatic test pattern generation; Circuit faults; Circuit testing; Combinational circuits; Compaction; Delay; Fault detection; Heuristic algorithms; Sequential analysis; Sequential circuits; delay test; dynamic compaction; path delay fault; test generation;
Conference_Titel :
VLSI Test Symposium, 2008. VTS 2008. 26th IEEE
Conference_Location :
San Diego, CA
Print_ISBN :
978-0-7695-3123-6
DOI :
10.1109/VTS.2008.54
