DocumentCode
3373534
Title
High etch rate and low temperature InP backside via etching using HI-based inductively coupled plasma
Author
Kotani, Kenji ; Kawasaki, Takeshi ; Miyazaki, Tomihito ; Yaegassi, Seiji ; Yano, Hiroshi
Author_Institution
Transmission Device R&D Labs., Sumitomo Electr. Ind. Ltd., Yokohama, Japan
fYear
2004
fDate
31 May-4 June 2004
Firstpage
717
Lastpage
720
Abstract
We have successfully demonstrated a high etch rate and low temperature backside via etching into InP using HI-based ICP. An average InP etch rate of 2.0 μm/min at a wafer temperature of 130 °C was obtained. Using this etching, 80 μm diameter backside vias were formed into 100 μm thick InP with a simple process. The vias show good profile and smooth surface over a 3-inch diameter wafer. From s-parameter measurements, the average via inductance of 12.1 pH was extracted and the inductance coincides with a calculated value. To evaluate reliability, a heat cycle test under a condition of temperature cycling from 150°C to -65°C was carried out. After testing of 100 cycles, all vias satisfied the test requirements. These results show that our InP backside via process is promising for practical applications.
Keywords
III-V semiconductors; etching; indium compounds; inductance; pH; surface roughness; 100 mum; 150 to -65 degC; 80 mum; HI; HI-based inductively coupled plasma; InP; backside via etching; etch rate; heat cycle test; inductance; pH; reliability; s-parameter measurements; surface smoothness; Couplings; Etching; HEMTs; Indium phosphide; MODFETs; Plasma applications; Plasma devices; Plasma temperature; Resists; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Indium Phosphide and Related Materials, 2004. 16th IPRM. 2004 International Conference on
ISSN
1092-8669
Print_ISBN
0-7803-8595-0
Type
conf
DOI
10.1109/ICIPRM.2004.1442826
Filename
1442826
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