Shifting time waveform induced CMOS latch up in bootstrapping technique applications

In this study, latch-up mechanisms of the complementary-metal-oxide-semiconductor (CMOS) in bootstrapping technique applied to DC/DC buck converter circuit has been clearly investigated by two dimensional (2D) TCAD simulations. The shifting times of input signal waveforms were demonstrated to be the key factor to induce the CMOS latch-up due to the triggering of parasitic bipolar junction transistors (BJTs) in the CMOS bootstrapping application. In addition, the free latch-up design window suggests that both of the larger rise time and longer shifting times of input signal waveforms will provide a larger safety operation region for circuit design engineers in this work.