• DocumentCode
    3373564
  • Title

    Width-constrained wire sizing for non-tree interconnections

  • Author

    Chen, Zhi-Wei ; Yan, Jin-Tai

  • Author_Institution
    Coll. of Eng., Chung-Hua Univ., Hsinchu, Taiwan
  • fYear
    2010
  • fDate
    May 30 2010-June 2 2010
  • Firstpage
    2586
  • Lastpage
    2589
  • Abstract
    With the use of non-tree topology in signal nets, the delay issue in non-tree topologies has become an important problem. In this paper, based on the transformation-based timing analysis for a non-tree interconnection, an iterative wire-sizing approach is proposed to assign feasible widths onto the wire segments to minimize the timing delay in the critical path for a non-tree interconnection under a maximum-width constraint Compared with the original non-tree interconnection with the assignment of minimum width, the experimental results show that our proposed approach achieves 15.6%, 19.6% and 22.1% of delay reduction on the average under 0.36μm, O.S4μm and ft 72fan maximum-width constraints, respectively.
  • Keywords
    integrated circuit design; integrated circuit interconnections; critical path; delay issue; iterative wire-sizing; maximum-width constraint; nontree interconnection; nontree topologies; nontree topology; signal nets; timing delay; transformation-based timing analysis; width-constrained wire sizing; Capacitance; Clocks; Delay; Iterative methods; Protection; Routing; Timing; Topology; Wire; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
  • Conference_Location
    Paris
  • Print_ISBN
    978-1-4244-5308-5
  • Electronic_ISBN
    978-1-4244-5309-2
  • Type

    conf

  • DOI
    10.1109/ISCAS.2010.5537104
  • Filename
    5537104