Dynamic degradation mechanisms of low temperature polycrystalline silicon thin-film transistors

Degradation mechanisms of low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) under various dynamic stresses are reviewed. Dynamic hot carrier (HC) mechanism under gate and drain stress pulses is interpreted based on non-equilibrium PN junction model. For synchronized gate and drain stress pulse, both dynamic HC and self-heating (SH) mechanism are involved. For n-type TFTs, device degradation is dominated by SH at low-frequencies whereas by dynamic HC at high frequencies. Besides, for p-type TFTs, negative bias temperature instability and the dynamic HC mechanisms are both effective for the degradation.