Wafer-level characterization of EEPROM tunnel oxide using a fast floating-gate technique and a realistic memory cell-based test structure

Author

Renard, Sophie ; Boivin, Philippe ; Autran, Jean-Luc

Author_Institution

Zone Industrielle de Rousset, STMicroelectronics, Rousset, France

fYear

2002

fDate

8-11 April 2002

Firstpage

145

Lastpage

150

Abstract

We report on the development of a fast characterization technique of EEPROM tunnel oxides based on the floating-gate technique and using a realistic memory cell-based test structure. A sequential measurement procedure and data analysis have been successfully implemented to perform automatic wafer screening of leakage currents in terms of charge retention and tunnel oxide defectivity.

Keywords

EPROM; MOS capacitors; MOSFET; integrated circuit measurement; integrated circuit reliability; integrated circuit testing; leakage currents; tunnelling; EEPROM tunnel oxide; automatic wafer screening; charge retention; data analysis; fast characterization technique; fast floating-gate technique; large area tunnel oxide capacitor; leakage currents; memory cell-based test structure; n-channel MOS native transistor; realistic memory cell-based test structure; sequential measurement procedure; tunnel oxide defectivity; wafer-level characterization; Charge measurement; Current measurement; EPROM; Leakage current; Loss measurement; MOS capacitors; Nonvolatile memory; Performance evaluation; Temperature; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2002. ICMTS 2002. Proceedings of the 2002 International Conference on

Print_ISBN

0-7803-7464-9

Type

conf

DOI

10.1109/ICMTS.2002.1193187

Filename

1193187