Title :
Automatic partitioning for deterministic test
Author :
Crestani, D. ; Aguila, A. ; Gentil, M.-H. ; Chardon, P. ; Durante, C.
Author_Institution :
UMR CNRS, Montpellier II Univ., France
Abstract :
Automatic partitioning for digital circuits is proposed. The partitions are defined by using functional testability measures and a test difficulty estimation. The software, developed with an expert system generator, is embedded in a hierarchical test generation process. The partitioning technique proposed uses difficulty test estimation corresponding to the maximal number of logical gates that can be embedded in a given partition. This parameter represents the maximal number of gates that can be handled by the tool
Keywords :
automatic testing; expert systems; logic testing; automatic partitioning; deterministic test; digital circuits; expert system generator; functional testability; hierarchical test generation process; logical gates; software; test difficulty estimation; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Controllability; Digital circuits; Observability; Phase estimation; Robotics and automation; System testing;
Conference_Titel :
Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-2780-8
DOI :
10.1109/EURDAC.1992.246224
