• DocumentCode
    3374971
  • Title

    Efficient constrained encoding for VLSI sequential logic synthesis

  • Author

    Shi, C.-J. ; Brzozowski, J.A.

  • Author_Institution
    Dept. of Comput. Sci., Waterloo Univ., Ont., Canada
  • fYear
    1992
  • fDate
    7-10 Sep 1992
  • Firstpage
    266
  • Lastpage
    271
  • Abstract
    A fast heuristic algorithm called ENCORE is proposed for the dichotomy-based constrained encoding problem. Its implementation has been tested on MCNC synchronous sequential logic benchmarks. For the case of complete encoding, ENCORE generates the same or shorter encoding lengths than the programs KISS, NOVA and DIET, for most of the benchmarks, and uses much less CPU time. For bounded-length encoding, ENCORE produces better overall quality than both random encoding and NOVA. ENCORE has also been applied to state assignment problems for asynchronous machines; it consistently obtains optimal or near-optimal results for a variety of examples found in the literature
  • Keywords
    VLSI; asynchronous sequential logic; encoding; logic CAD; logic testing; sequential circuits; state assignment; DIET; ENCORE; KISS; MCNC synchronous sequential logic benchmarks; NOVA; VLSI sequential logic synthesis; asynchronous machines; constrained encoding; dichotomy-based; heuristic algorithm; state assignment; Benchmark testing; Circuit synthesis; Computer science; Delay; Encoding; Heuristic algorithms; Logic testing; Minimization; Programmable logic arrays; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
  • Conference_Location
    Hamburg
  • Print_ISBN
    0-8186-2780-8
  • Type

    conf

  • DOI
    10.1109/EURDAC.1992.246233
  • Filename
    246233