Cellular nanoscale network cell with memristors for local implication logic and synapses

This paper describes a cellular nanoscale network cell structure that is aimed to be built as a CMOS-nanomemristor hybrid. The processing cell uses memristors as ON-OFF programmable synapses, local logic and memory. Local logic is based on memristor computations using material implication. Only 15 CMOS transistors per cell are used, independent of the size of the neighborhood, since memristors are used as synapses. Also, space-dependent templates (weight matrices) are possible at no extra hardware cost. The operation of the cell is described and simulation results are shown to illustrate the operation.