Title :
Low-cost low-power bypassing-based multiplier design
Author :
Yan, Jin-Tai ; Chen, Zhi-Wei
Author_Institution :
Dept. of Comput. Sci. & Inf., Chung-Hua Univ., Hsinchu, Taiwan
fDate :
May 30 2010-June 2 2010
Abstract :
Based on the simplification of the addition operations in a low-power bypassing-based multiplier, a low-cost low-power bypassing-based multiplier is proposed Compared with row-bypassing multiplier, column-bypassing multiplier and 2-dimensional bypassing-based multiplier for 20 tested examples, the experimental results show that our proposed low-cost low-power multiplier saves 15.1% of hardware cost and reduces 29.6% of the power dissipation on the average for 4×4, 8×8 and 16×16 multipliers.
Keywords :
adders; integrated circuit design; low-power electronics; multiplying circuits; 2-dimensional bypassing-based multiplier; addition operation; column-bypassing multiplier; low-cost low-power bypassing-based multiplier design; power dissipation; row-bypassing multiplier; Birth disorders; Capacitance; Circuits; Clocks; Computer science; Design engineering; Digital signal processing; Hardware; Power dissipation; Testing;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537190
