Title :
P.Size: a sizing aid for optimized designs
Author :
Azemard, N. ; Bonzom, V. ; Auvergne, D.
Author_Institution :
LIRMM, Montpellier, France
Abstract :
Transistor sizing at layout level is necessary to improve the overall performance of integrated circuits. The authors present the definition and the validation of a sizing aid, P.Size, integrated in a flexible cell generator. Based on a local optimization defined through an explicit formulation of delays, this sizing aid can be used to optimize real data paths, under constraint, with few CPU time requirements. Validations, through comparison with a mathematical optimization procedure and an industrial optimizer, are given
Keywords :
VLSI; circuit layout CAD; optimisation; CPU time requirements; P.Size; VLSI; delays; flexible cell generator; industrial optimizer; layout level; local optimization; mathematical optimization procedure; optimized designs; performance of integrated circuits; real data paths; sizing aid; Central Processing Unit; Circuit optimization; Constraint optimization; Delay effects; Design optimization; Fabrication; Integrated circuit layout; Optimization methods; Performance evaluation; Robots;
Conference_Titel :
Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-2780-8
DOI :
10.1109/EURDAC.1992.246248
