• DocumentCode
    3375362
  • Title

    Reduction of Energy Consumption in Processors by Early Detection and Bypassing of Trivial Operations

  • Author

    Islam, Md Mafijul ; Stenstrom, Per

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Chalmers Univ. of Technol., Goteborg
  • fYear
    2006
  • fDate
    38899
  • Firstpage
    28
  • Lastpage
    34
  • Abstract
    Previous research has established that trivial operations, i.e., instructions whose outcome can be trivially inferred from the operands, e.g. addition of zero, account for a quite significant portion of the dynamically executed instructions. By detecting them early and removing them from the pipeline, it is possible to reduce the energy consumption. This paper first presents a new classification of trivial operations in which especially such trivial operations that can be detected early, i.e. at the decode stage, in the pipeline are identified. Our analysis shows that on average as many as 10% of all executed instructions are of this kind across 12 applications from SPEC2000. We find that a majority (indeed 89%) of them are identity-trivial in which at least one of the operands is the identity element - zero or one. By detecting them early, one can bypass their execution and eliminate register accesses if the processor uses a logical/physical register remapping unit. We find that as many as 75% of all trivial operations can be detected and eliminated at the decode stage because the identity element is available that often. With such support, we find that the energy consumption in the functional units, the result bus, the instruction window infrastructure, and the register file can be reduced by 13%, 9%, 27%, and 26%, respectively yielding 18% reduction of the energy in the core pipeline
  • Keywords
    decoding; file organisation; instruction sets; pipeline processing; power aware computing; energy consumption reduction; pipeline identification; register file remapping unit; trivial operation detection; Computer aided instruction; Computer science; Decoding; Energy consumption; Optimizing compilers; Performance gain; Pipelines; Power engineering and energy; Program processors; Registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Embedded Computer Systems: Architectures, Modeling and Simulation, 2006. IC-SAMOS 2006. International Conference on
  • Conference_Location
    Samos
  • Print_ISBN
    1-4244-0155-0
  • Type

    conf

  • DOI
    10.1109/ICSAMOS.2006.300805
  • Filename
    4084746