Title :
A 20-V p-channel with 650 μΩ-cm2 at VGS =2.7 V: Overcoming FPI breakdown in high-channel-conductance low-V t trenchFETs
Author :
Williams, Richard K. ; Grabowski, W. ; Berwick, Jeff ; Darwish, Mahmoud ; Chang, Mingchao
Author_Institution :
Siliconix Inc., Santa Clara, CA, USA
Abstract :
A 5 Mcell/cm2 (32 Mcell/in2) low-threshold 20-V p-channel trenchFET (U-groove trench-gated DMOSFET) is reported, achieving specific on-resistances of 450, 650 and 720 μΩ-cm2 at VGS biases of 4.5, 2.7 and 2.5 V, respectively. A distributed 1-of-n avalanche voltage clamp is employed to achieve high cell densities and high channel conductance, while mitigating field plate induced (FPI) breakdown associated with scaled (12 V maximum rated) trench gate oxides. The measured on-resistance, which is 60% of that of a prior generation 1.9 Mcell/cm 2 design, represents the lowest reported p-channel specific on-resistance
Keywords :
dielectric thin films; electric admittance; electric breakdown; electric resistance; isolation technology; power MOSFET; semiconductor device models; semiconductor device testing; 12 V; 2.5 V; 2.7 V; 20 V; 4.5 V; FPI breakdown; U-groove trench-gated DMOSFET; cell density; channel conductance; distributed 1-of-n avalanche voltage clamp; field plate induced breakdown; gate bias voltage; high channel conductance trenchFETs; low threshold trenchFETs; on-resistance; p-channel; p-channel specific on-resistance; p-channel trenchFET; scaled trench gate oxides; specific on-resistance; trenchFETs; Avalanche breakdown; Batteries; Breakdown voltage; Clamps; Diodes; Electric breakdown; Impact ionization; MOSFETs; Portable computers; Power semiconductor switches;
Conference_Titel :
Power Semiconductor Devices and ICs, 1998. ISPSD 98. Proceedings of the 10th International Symposium on
Conference_Location :
Kyoto
Print_ISBN :
0-7803-4752-8
DOI :
10.1109/ISPSD.1998.702733
