DESB, a functional abstractor for CMOS VLSI circuits

DESB is included in a set of tools for hierarchical verification of custom VLSI circuits. These tools include the layout extractor DAX, DESB, the electrical rule checker VERTEC, and the timing analyzer TAS. The functional abstractor DESB is the key point in a hierarchical verification process. A functional abstractor for CMOS VLSI circuits is presented. A gate-level descriptions is derived from a transistor-level description of the circuit, and the logic equations are then expressed in behavioral VHSIC description language (VHDL). These tools do not employ any cell library. The models used and implemented in DESB are described