Title :
Design of delay insensitive circuits using multi-ring structures
Author :
Sparso, J. ; Staunstrup, Jørgen ; Dantzer-Sorensen, M.
Author_Institution :
Dept. of Comput. Sci., Tech. Univ. of Denmark, Lyngby, Denmark
Abstract :
The design and VLSI implementation of a delay insensitive circuit that computes the inner product of two vec·tors is described. The circuit is based on an iterative serial-parallel multiplication algorithm. The design is based on a data flow approach using pipelines and rings that are combined into larger multi ring structures by the joining and forking of signals. The implementation is based on a small set of building blocks (latches, combinational circuits and switches) that are composed of C-elements and simple gates. By following this approach, delay insensitive circuits with nontrivial functionality and reasonable performance are readily designed
Keywords :
VLSI; asynchronous sequential logic; delays; integrated logic circuits; logic design; C-elements; VLSI implementation; building blocks; combinational circuits; data flow approach; delay insensitive circuits design; inner product; iterative serial-parallel multiplication algorithm; latches; nontrivial functionality; switches; Buildings; Circuit testing; Clocks; Computer science; Delay; Design automation; Encoding; Iterative algorithms; Signal design; Very large scale integration;
Conference_Titel :
Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-2780-8
DOI :
10.1109/EURDAC.1992.246271
