The anatomy of the register file in a multiscalar processor

Author

Breach, Scott E. ; Vijaykumar, T.N. ; Sohi, Gurindar S.

Author_Institution

Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA

fYear

1994

fDate

30 Nov.-2 Dec. 1994

Firstpage

181

Lastpage

190

Abstract

This paper presents the operation of the register file in the multiscalar architecture. The register file provides the appearance of a logically centralized register file, yet is implemented as physically decentralized register files, queues, and control logic in a multiscalar processor. We address the key issues of storage, communication, and synchronization required for a successful design and discuss the complications that arise in the face of speculation. In particular, the hardware required to implement the register file is detailed, and software support to streamline the operation of the register file is described. Illustrative examples detailing important aspects of the operation of the register file and an evaluation of its effectiveness are provided.

Keywords

instruction sets; parallel architectures; program compilers; synchronisation; communication; compiler support; control logic; decentralized register file; instruction-level parallelism; logically centralized register file; multiscalar architecture; multiscalar processor; queues; register file; storage; synchronization; Anatomy; Centralized control; Communication system control; Computer architecture; Distributed computing; Engines; Logic; Parallel processing; Permission; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Microarchitecture, 1994. MICRO-27. Proceedings of the 27th Annual International Symposium on

ISSN

1072-4451

Print_ISBN

0-89791-707-3

Type

conf

DOI

10.1109/MICRO.1994.717457

Filename

717457