A 2.4-GHz reference doubled fractional-N PLL with dual phase detector in 0.13-μm CMOS

This paper presents a low noise fractional-N PLL that employs the reference multiplication technique. In order to reduce the noise from ΔΣ modulator (DSM) and charge-pump (CP), the proposed PLL increases the OSR of the DSM and reduces the gain of the CP to the output It employs dual phase detector (PD) architecture that can obtain the information of the phase error twice more frequently than a conventional PLL. The prototype chip implemented in 0.13 μm CMOS process achieves 3 dB and 9 dB improvement of phase noise at 10 kHz and 2 MHz offset respectively. It consumes 4.2 mW at 1.2 V supply and occupies 0.23 mm² which are 15 % and 4 % increased in power and area respectively compared to the conventional PLL.