• DocumentCode
    3376567
  • Title

    A scalable quantitative measure of IR-drop effects for scan pattern generation

  • Author

    Wu, M.-F. ; Tsai, Kun-Han ; Cheng, Wu-Tung ; Pan, H.-C. ; Huang, Jiun-Lang ; Kifli, Augusli

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • fYear
    2010
  • fDate
    7-11 Nov. 2010
  • Firstpage
    162
  • Lastpage
    167
  • Abstract
    Analysis of power grid IR-drop during scan test application has drawn growing attention because excessive IR-drop may cause a functionally correct device to fail at-speed testing. The analysis is challenging since the power grid IR-drop profile depends on not only the switching cells locations but also the power grid structure. This paper presents a scalable implementation methodology for quantifying the IR-drop effects of a set of switching cells. An example of its application to guide power-safe scan pattern generation is illustrated. The scalability and effectiveness of the proposed quantitative measure is evaluated with a 130 nm industrial design with 800 K cells.
  • Keywords
    automatic test pattern generation; integrated circuit testing; logic arrays; switching circuits; IR drop effect; power grid IR drop; power safe scan pattern generation; scalable implementation methodology; size 130 nm; speed testing; switching cell location; Automatic test pattern generation; Computer architecture; Microprocessors; Power grids; Scalability; Sparse matrices; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA
  • ISSN
    1092-3152
  • Print_ISBN
    978-1-4244-8193-4
  • Type

    conf

  • DOI
    10.1109/ICCAD.2010.5654130
  • Filename
    5654130