Subthreshold current mode matrix determinant computation for analog signal processing

Author

Kim, Stephen T. ; Choi, Jaehyouk ; Beck, Sungho ; Song, Taejoong ; Lim, Kyutae ; Laskar, Joy

Author_Institution

Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2010

fDate

May 30 2010-June 2 2010

Firstpage

1260

Lastpage

1263

Abstract

The matrix determinant computation system (MDCS) is developed in subthreshold current-mode for an analog signal processing. By utilizing the translinear loop principle and the novel differential architecture, the MDCS can perform accurate addition, subtraction, and multiplication in analog domain. The system computes a 2-by-2 and 3-by-3 determinant with 91 % accuracy and a 3 kHz input can be handled while consuming 110.05μW. The overall system is fabricated on a 0.18μm CMOS technology and the area is 500μm × 800μm.

Keywords

CMOS analogue integrated circuits; matrix algebra; signal processing; CMOS technology; MDCS; analog signal processing; differential architecture; frequency 3 kHz; power 110.05 muW; subthreshold current mode matrix determinant computation; translinear loop principle; Analog computers; CMOS technology; Computer architecture; Degradation; Digital signal processing; Energy consumption; Signal processing; Signal processing algorithms; Signal resolution; Subthreshold current;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Conference_Location

Paris

Print_ISBN

978-1-4244-5308-5

Electronic_ISBN

978-1-4244-5309-2

Type

conf

DOI

10.1109/ISCAS.2010.5537276

Filename

5537276