Scheduling of synchronous data flow models on scratchpad memory based embedded processors

Many embedded processors incorporate scratchpad memories (SPM) due to their lower power consumption characteristics. SPMs are utilized to host both code and data, often on the same physical unit. Synchronous dataflow (SDF) is a popular format for specifying many embedded system applications particularly in multimedia and network processing domains. Execution of SDF specifications on SPM based processors involves division of memory between actor code and buffers, and scheduling of actor executions and code overlays such that latency is minimized subject to the memory constraints. In our problem instance a traditional minimum buffer SDF schedule could require a larger code overlay overhead and therefore may not be optimal. The paper presents a three stage integer linear programming (ILP) formulation to solve the problem. Further, the paper also introduces modifications to the three stage ILP for incorporating code prefetching optimization to further reduce the code overlay overhead. The effectiveness of the proposed approaches is evaluated by comparisons with minimum buffer SDF schedules for several benchmark applications.