Low power and less complex implementation of fast block LMS adaptive filter using distributed arithmetic

This paper presents the design and implementation of an efficient fast block least mean squares (FBLMS) based adaptive digital filter. The proposed implementation is based on distributed arithmetic (DA), which substitutes multiply-and-accumulate operations with a series of look-up-tables (LUT). Thus, the proposed implementation is highly power and area efficient. This can be achieved at the cost of a moderate increase in memory usage. Furthermore, the fundamental building blocks in the DA architecture map well to the architecture of todays Field Programmable Gate Arrays (FPGA). In this paper, we analyze the design of an FBLMS algorithm based adaptive filter. FPGA implementation results conforms that the proposed DA based adaptive filter can implement with significantly smaller area usage, (about 52%) less than that of the existing FBLMS algorithm based adaptive filter implementations.